stm32f10x_i2c.h 29 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f10x_i2c.h
  4. * @author MCD Application Team
  5. * @version V3.5.0
  6. * @date 11-March-2011
  7. * @brief This file contains all the functions prototypes for the I2C firmware
  8. * library.
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  20. ******************************************************************************
  21. */
  22. /* Define to prevent recursive inclusion -------------------------------------*/
  23. #ifndef __STM32F10x_I2C_H
  24. #define __STM32F10x_I2C_H
  25. #ifdef __cplusplus
  26. extern "C" {
  27. #endif
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f10x.h"
  30. /** @addtogroup STM32F10x_StdPeriph_Driver
  31. * @{
  32. */
  33. /** @addtogroup I2C
  34. * @{
  35. */
  36. /** @defgroup I2C_Exported_Types
  37. * @{
  38. */
  39. /**
  40. * @brief I2C Init structure definition
  41. */
  42. typedef struct
  43. {
  44. uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
  45. This parameter must be set to a value lower than 400kHz */
  46. uint16_t I2C_Mode; /*!< Specifies the I2C mode.
  47. This parameter can be a value of @ref I2C_mode */
  48. uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
  49. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
  50. uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
  51. This parameter can be a 7-bit or 10-bit address. */
  52. uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
  53. This parameter can be a value of @ref I2C_acknowledgement */
  54. uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
  55. This parameter can be a value of @ref I2C_acknowledged_address */
  56. }I2C_InitTypeDef;
  57. /**
  58. * @}
  59. */
  60. /** @defgroup I2C_Exported_Constants
  61. * @{
  62. */
  63. #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
  64. ((PERIPH) == I2C2))
  65. /** @defgroup I2C_mode
  66. * @{
  67. */
  68. #define I2C_Mode_I2C ((uint16_t)0x0000)
  69. #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
  70. #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
  71. #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
  72. ((MODE) == I2C_Mode_SMBusDevice) || \
  73. ((MODE) == I2C_Mode_SMBusHost))
  74. /**
  75. * @}
  76. */
  77. /** @defgroup I2C_duty_cycle_in_fast_mode
  78. * @{
  79. */
  80. #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
  81. #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
  82. #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
  83. ((CYCLE) == I2C_DutyCycle_2))
  84. /**
  85. * @}
  86. */
  87. /** @defgroup I2C_acknowledgement
  88. * @{
  89. */
  90. #define I2C_Ack_Enable ((uint16_t)0x0400)
  91. #define I2C_Ack_Disable ((uint16_t)0x0000)
  92. #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
  93. ((STATE) == I2C_Ack_Disable))
  94. /**
  95. * @}
  96. */
  97. /** @defgroup I2C_transfer_direction
  98. * @{
  99. */
  100. #define I2C_Direction_Transmitter ((uint8_t)0x00)
  101. #define I2C_Direction_Receiver ((uint8_t)0x01)
  102. #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
  103. ((DIRECTION) == I2C_Direction_Receiver))
  104. /**
  105. * @}
  106. */
  107. /** @defgroup I2C_acknowledged_address
  108. * @{
  109. */
  110. #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
  111. #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
  112. #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
  113. ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
  114. /**
  115. * @}
  116. */
  117. /** @defgroup I2C_registers
  118. * @{
  119. */
  120. #define I2C_Register_CR1 ((uint8_t)0x00)
  121. #define I2C_Register_CR2 ((uint8_t)0x04)
  122. #define I2C_Register_OAR1 ((uint8_t)0x08)
  123. #define I2C_Register_OAR2 ((uint8_t)0x0C)
  124. #define I2C_Register_DR ((uint8_t)0x10)
  125. #define I2C_Register_SR1 ((uint8_t)0x14)
  126. #define I2C_Register_SR2 ((uint8_t)0x18)
  127. #define I2C_Register_CCR ((uint8_t)0x1C)
  128. #define I2C_Register_TRISE ((uint8_t)0x20)
  129. #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
  130. ((REGISTER) == I2C_Register_CR2) || \
  131. ((REGISTER) == I2C_Register_OAR1) || \
  132. ((REGISTER) == I2C_Register_OAR2) || \
  133. ((REGISTER) == I2C_Register_DR) || \
  134. ((REGISTER) == I2C_Register_SR1) || \
  135. ((REGISTER) == I2C_Register_SR2) || \
  136. ((REGISTER) == I2C_Register_CCR) || \
  137. ((REGISTER) == I2C_Register_TRISE))
  138. /**
  139. * @}
  140. */
  141. /** @defgroup I2C_SMBus_alert_pin_level
  142. * @{
  143. */
  144. #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
  145. #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
  146. #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
  147. ((ALERT) == I2C_SMBusAlert_High))
  148. /**
  149. * @}
  150. */
  151. /** @defgroup I2C_PEC_position
  152. * @{
  153. */
  154. #define I2C_PECPosition_Next ((uint16_t)0x0800)
  155. #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
  156. #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
  157. ((POSITION) == I2C_PECPosition_Current))
  158. /**
  159. * @}
  160. */
  161. /** @defgroup I2C_NCAK_position
  162. * @{
  163. */
  164. #define I2C_NACKPosition_Next ((uint16_t)0x0800)
  165. #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
  166. #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
  167. ((POSITION) == I2C_NACKPosition_Current))
  168. /**
  169. * @}
  170. */
  171. /** @defgroup I2C_interrupts_definition
  172. * @{
  173. */
  174. #define I2C_IT_BUF ((uint16_t)0x0400)
  175. #define I2C_IT_EVT ((uint16_t)0x0200)
  176. #define I2C_IT_ERR ((uint16_t)0x0100)
  177. #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
  178. /**
  179. * @}
  180. */
  181. /** @defgroup I2C_interrupts_definition
  182. * @{
  183. */
  184. #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
  185. #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
  186. #define I2C_IT_PECERR ((uint32_t)0x01001000)
  187. #define I2C_IT_OVR ((uint32_t)0x01000800)
  188. #define I2C_IT_AF ((uint32_t)0x01000400)
  189. #define I2C_IT_ARLO ((uint32_t)0x01000200)
  190. #define I2C_IT_BERR ((uint32_t)0x01000100)
  191. #define I2C_IT_TXE ((uint32_t)0x06000080)
  192. #define I2C_IT_RXNE ((uint32_t)0x06000040)
  193. #define I2C_IT_STOPF ((uint32_t)0x02000010)
  194. #define I2C_IT_ADD10 ((uint32_t)0x02000008)
  195. #define I2C_IT_BTF ((uint32_t)0x02000004)
  196. #define I2C_IT_ADDR ((uint32_t)0x02000002)
  197. #define I2C_IT_SB ((uint32_t)0x02000001)
  198. #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
  199. #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
  200. ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
  201. ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
  202. ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
  203. ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
  204. ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
  205. ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
  206. /**
  207. * @}
  208. */
  209. /** @defgroup I2C_flags_definition
  210. * @{
  211. */
  212. /**
  213. * @brief SR2 register flags
  214. */
  215. #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
  216. #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
  217. #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
  218. #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
  219. #define I2C_FLAG_TRA ((uint32_t)0x00040000)
  220. #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
  221. #define I2C_FLAG_MSL ((uint32_t)0x00010000)
  222. /**
  223. * @brief SR1 register flags
  224. */
  225. #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
  226. #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
  227. #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
  228. #define I2C_FLAG_OVR ((uint32_t)0x10000800)
  229. #define I2C_FLAG_AF ((uint32_t)0x10000400)
  230. #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
  231. #define I2C_FLAG_BERR ((uint32_t)0x10000100)
  232. #define I2C_FLAG_TXE ((uint32_t)0x10000080)
  233. #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
  234. #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
  235. #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
  236. #define I2C_FLAG_BTF ((uint32_t)0x10000004)
  237. #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
  238. #define I2C_FLAG_SB ((uint32_t)0x10000001)
  239. #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
  240. #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
  241. ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
  242. ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
  243. ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
  244. ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
  245. ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
  246. ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
  247. ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
  248. ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
  249. ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
  250. ((FLAG) == I2C_FLAG_SB))
  251. /**
  252. * @}
  253. */
  254. /** @defgroup I2C_Events
  255. * @{
  256. */
  257. /*========================================
  258. I2C Master Events (Events grouped in order of communication)
  259. ==========================================*/
  260. /**
  261. * @brief Communication start
  262. *
  263. * After sending the START condition (I2C_GenerateSTART() function) the master
  264. * has to wait for this event. It means that the Start condition has been correctly
  265. * released on the I2C bus (the bus is free, no other devices is communicating).
  266. *
  267. */
  268. /* --EV5 */
  269. #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
  270. /**
  271. * @brief Address Acknowledge
  272. *
  273. * After checking on EV5 (start condition correctly released on the bus), the
  274. * master sends the address of the slave(s) with which it will communicate
  275. * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
  276. * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
  277. * his address. If an acknowledge is sent on the bus, one of the following events will
  278. * be set:
  279. *
  280. * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
  281. * event is set.
  282. *
  283. * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
  284. * is set
  285. *
  286. * 3) In case of 10-Bit addressing mode, the master (just after generating the START
  287. * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
  288. * function). Then master should wait on EV9. It means that the 10-bit addressing
  289. * header has been correctly sent on the bus. Then master should send the second part of
  290. * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
  291. * should wait for event EV6.
  292. *
  293. */
  294. /* --EV6 */
  295. #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
  296. #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
  297. /* --EV9 */
  298. #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
  299. /**
  300. * @brief Communication events
  301. *
  302. * If a communication is established (START condition generated and slave address
  303. * acknowledged) then the master has to check on one of the following events for
  304. * communication procedures:
  305. *
  306. * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
  307. * the data received from the slave (I2C_ReceiveData() function).
  308. *
  309. * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
  310. * function) then to wait on event EV8 or EV8_2.
  311. * These two events are similar:
  312. * - EV8 means that the data has been written in the data register and is
  313. * being shifted out.
  314. * - EV8_2 means that the data has been physically shifted out and output
  315. * on the bus.
  316. * In most cases, using EV8 is sufficient for the application.
  317. * Using EV8_2 leads to a slower communication but ensure more reliable test.
  318. * EV8_2 is also more suitable than EV8 for testing on the last data transmission
  319. * (before Stop condition generation).
  320. *
  321. * @note In case the user software does not guarantee that this event EV7 is
  322. * managed before the current byte end of transfer, then user may check on EV7
  323. * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
  324. * In this case the communication may be slower.
  325. *
  326. */
  327. /* Master RECEIVER mode -----------------------------*/
  328. /* --EV7 */
  329. #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
  330. /* Master TRANSMITTER mode --------------------------*/
  331. /* --EV8 */
  332. #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
  333. /* --EV8_2 */
  334. #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
  335. /*========================================
  336. I2C Slave Events (Events grouped in order of communication)
  337. ==========================================*/
  338. /**
  339. * @brief Communication start events
  340. *
  341. * Wait on one of these events at the start of the communication. It means that
  342. * the I2C peripheral detected a Start condition on the bus (generated by master
  343. * device) followed by the peripheral address. The peripheral generates an ACK
  344. * condition on the bus (if the acknowledge feature is enabled through function
  345. * I2C_AcknowledgeConfig()) and the events listed above are set :
  346. *
  347. * 1) In normal case (only one address managed by the slave), when the address
  348. * sent by the master matches the own address of the peripheral (configured by
  349. * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
  350. * (where XXX could be TRANSMITTER or RECEIVER).
  351. *
  352. * 2) In case the address sent by the master matches the second address of the
  353. * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
  354. * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
  355. * (where XXX could be TRANSMITTER or RECEIVER) are set.
  356. *
  357. * 3) In case the address sent by the master is General Call (address 0x00) and
  358. * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
  359. * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
  360. *
  361. */
  362. /* --EV1 (all the events below are variants of EV1) */
  363. /* 1) Case of One Single Address managed by the slave */
  364. #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
  365. #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
  366. /* 2) Case of Dual address managed by the slave */
  367. #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
  368. #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
  369. /* 3) Case of General Call enabled for the slave */
  370. #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
  371. /**
  372. * @brief Communication events
  373. *
  374. * Wait on one of these events when EV1 has already been checked and:
  375. *
  376. * - Slave RECEIVER mode:
  377. * - EV2: When the application is expecting a data byte to be received.
  378. * - EV4: When the application is expecting the end of the communication: master
  379. * sends a stop condition and data transmission is stopped.
  380. *
  381. * - Slave Transmitter mode:
  382. * - EV3: When a byte has been transmitted by the slave and the application is expecting
  383. * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
  384. * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
  385. * used when the user software doesn't guarantee the EV3 is managed before the
  386. * current byte end of transfer.
  387. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
  388. * shall end (before sending the STOP condition). In this case slave has to stop sending
  389. * data bytes and expect a Stop condition on the bus.
  390. *
  391. * @note In case the user software does not guarantee that the event EV2 is
  392. * managed before the current byte end of transfer, then user may check on EV2
  393. * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
  394. * In this case the communication may be slower.
  395. *
  396. */
  397. /* Slave RECEIVER mode --------------------------*/
  398. /* --EV2 */
  399. #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
  400. /* --EV4 */
  401. #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
  402. /* Slave TRANSMITTER mode -----------------------*/
  403. /* --EV3 */
  404. #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
  405. #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
  406. /* --EV3_2 */
  407. #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
  408. /*=========================== End of Events Description ==========================================*/
  409. #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
  410. ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
  411. ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
  412. ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
  413. ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
  414. ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
  415. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
  416. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
  417. ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
  418. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
  419. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
  420. ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
  421. ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
  422. ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
  423. ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
  424. ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
  425. ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
  426. ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
  427. ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
  428. ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
  429. /**
  430. * @}
  431. */
  432. /** @defgroup I2C_own_address1
  433. * @{
  434. */
  435. #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
  436. /**
  437. * @}
  438. */
  439. /** @defgroup I2C_clock_speed
  440. * @{
  441. */
  442. #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
  443. /**
  444. * @}
  445. */
  446. /**
  447. * @}
  448. */
  449. /** @defgroup I2C_Exported_Macros
  450. * @{
  451. */
  452. /**
  453. * @}
  454. */
  455. /** @defgroup I2C_Exported_Functions
  456. * @{
  457. */
  458. void I2C_DeInit(I2C_TypeDef* I2Cx);
  459. void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
  460. void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
  461. void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  462. void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  463. void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  464. void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
  465. void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
  466. void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
  467. void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
  468. void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  469. void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  470. void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
  471. void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
  472. uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
  473. void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
  474. uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
  475. void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  476. void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
  477. void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
  478. void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
  479. void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
  480. void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
  481. uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
  482. void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  483. void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  484. void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
  485. /**
  486. * @brief
  487. ****************************************************************************************
  488. *
  489. * I2C State Monitoring Functions
  490. *
  491. ****************************************************************************************
  492. * This I2C driver provides three different ways for I2C state monitoring
  493. * depending on the application requirements and constraints:
  494. *
  495. *
  496. * 1) Basic state monitoring:
  497. * Using I2C_CheckEvent() function:
  498. * It compares the status registers (SR1 and SR2) content to a given event
  499. * (can be the combination of one or more flags).
  500. * It returns SUCCESS if the current status includes the given flags
  501. * and returns ERROR if one or more flags are missing in the current status.
  502. * - When to use:
  503. * - This function is suitable for most applications as well as for startup
  504. * activity since the events are fully described in the product reference manual
  505. * (RM0008).
  506. * - It is also suitable for users who need to define their own events.
  507. * - Limitations:
  508. * - If an error occurs (ie. error flags are set besides to the monitored flags),
  509. * the I2C_CheckEvent() function may return SUCCESS despite the communication
  510. * hold or corrupted real state.
  511. * In this case, it is advised to use error interrupts to monitor the error
  512. * events and handle them in the interrupt IRQ handler.
  513. *
  514. * @note
  515. * For error management, it is advised to use the following functions:
  516. * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  517. * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
  518. * Where x is the peripheral instance (I2C1, I2C2 ...)
  519. * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
  520. * in order to determine which error occurred.
  521. * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
  522. * and/or I2C_GenerateStop() in order to clear the error flag and source,
  523. * and return to correct communication status.
  524. *
  525. *
  526. * 2) Advanced state monitoring:
  527. * Using the function I2C_GetLastEvent() which returns the image of both status
  528. * registers in a single word (uint32_t) (Status Register 2 value is shifted left
  529. * by 16 bits and concatenated to Status Register 1).
  530. * - When to use:
  531. * - This function is suitable for the same applications above but it allows to
  532. * overcome the limitations of I2C_GetFlagStatus() function (see below).
  533. * The returned value could be compared to events already defined in the
  534. * library (stm32f10x_i2c.h) or to custom values defined by user.
  535. * - This function is suitable when multiple flags are monitored at the same time.
  536. * - At the opposite of I2C_CheckEvent() function, this function allows user to
  537. * choose when an event is accepted (when all events flags are set and no
  538. * other flags are set or just when the needed flags are set like
  539. * I2C_CheckEvent() function).
  540. * - Limitations:
  541. * - User may need to define his own events.
  542. * - Same remark concerning the error management is applicable for this
  543. * function if user decides to check only regular communication flags (and
  544. * ignores error flags).
  545. *
  546. *
  547. * 3) Flag-based state monitoring:
  548. * Using the function I2C_GetFlagStatus() which simply returns the status of
  549. * one single flag (ie. I2C_FLAG_RXNE ...).
  550. * - When to use:
  551. * - This function could be used for specific applications or in debug phase.
  552. * - It is suitable when only one flag checking is needed (most I2C events
  553. * are monitored through multiple flags).
  554. * - Limitations:
  555. * - When calling this function, the Status register is accessed. Some flags are
  556. * cleared when the status register is accessed. So checking the status
  557. * of one Flag, may clear other ones.
  558. * - Function may need to be called twice or more in order to monitor one
  559. * single event.
  560. *
  561. */
  562. /**
  563. *
  564. * 1) Basic state monitoring
  565. *******************************************************************************
  566. */
  567. ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
  568. /**
  569. *
  570. * 2) Advanced state monitoring
  571. *******************************************************************************
  572. */
  573. uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
  574. /**
  575. *
  576. * 3) Flag-based state monitoring
  577. *******************************************************************************
  578. */
  579. FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
  580. /**
  581. *
  582. *******************************************************************************
  583. */
  584. void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
  585. ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
  586. void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
  587. #ifdef __cplusplus
  588. }
  589. #endif
  590. #endif /*__STM32F10x_I2C_H */
  591. /**
  592. * @}
  593. */
  594. /**
  595. * @}
  596. */
  597. /**
  598. * @}
  599. */
  600. /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/