/**
  ******************************************************************************
  * @file    system_stm32f10x.c
  * @author  MCD Application Team
  * @version V3.4.0
  * @date    10/15/2010
  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
  ******************************************************************************  
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/** @addtogroup CMSIS
  * @{
  */

/** @addtogroup stm32f10x_system
  * @{
  */  
  
/** @addtogroup STM32F10x_System_Private_Includes
  * @{
  */

#include "stm32f10x.h"
#include "main.h"

/**
  * @}
  */

/** @addtogroup STM32F10x_System_Private_TypesDefinitions
  * @{
  */

/**
  * @}
  */

/** @addtogroup STM32F10x_System_Private_Defines
  * @{
  */

/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
   frequency (after reset the HSI is used as SYSCLK source)
   
   IMPORTANT NOTE:
   ============== 
   1. After each device reset the HSI is used as System clock source.

   2. Please make sure that the selected System clock doesn't exceed your device's
      maximum frequency.
      
   3. If none of the define below is enabled, the HSI is used as System clock
    source.

   4. The System clock configuration functions provided within this file assume that:
        - For Low, Medium and High density Value line devices an external 8MHz 
          crystal is used to drive the System clock.
        - For Low, Medium and High density devices an external 8MHz crystal is
          used to drive the System clock.
        - For Connectivity line devices an external 25MHz crystal is used to drive
          the System clock.
     If you are using different crystal you have to adapt those functions accordingly.
    */
 static void SetSysClockTo48(void);
unsigned char g_ucHSE_Flag;//0--HSE Fail  1--HSE OK
#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
// #define SYSCLK_FREQ_24MHz  24000000
#else
/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
//file modify by wjl 20171109
#define SYSCLK_PREQ_USER
#define SYSCLK_PREQ_CLOCK   USER_MAIN_SYSCLK

#endif

/*!< Uncomment the following line if you need to use external SRAM mounted
     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
/* #define DATA_IN_ExtSRAM */
#endif

/*!< Uncomment the following line if you need to relocate your vector Table in
     Internal SRAM. */ 
/* #define VECT_TAB_SRAM */

#define VECT_TAB_OFFSET  0x4000 /*!< Vector Table base offset field. 
                                  This value must be a multiple of 0x100. */

/**
  * @}
  */

/** @addtogroup STM32F10x_System_Private_Macros
  * @{
  */

/**
  * @}
  */

/** @addtogroup STM32F10x_System_Private_Variables
  * @{
  */

/*******************************************************************************
*  Clock Definitions
*******************************************************************************/
#if defined SYSCLK_PREQ_USER
  uint32_t SystemCoreClock         = SYSCLK_PREQ_CLOCK;
#else /*!< HSI Selected as System Clock source */
  #error "Ç붨ÒåÏà¹ØʱÖÓÑ¡Ïî"
#endif

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
  * @}
  */

/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
  * @{
  */

static void SetSysClock(void);

#if defined SYSCLK_PREQ_USER
  static void SetSysClockToMy(void);
#endif

#ifdef DATA_IN_ExtSRAM
  static void SystemInit_ExtMemCtl(void); 
#endif /* DATA_IN_ExtSRAM */

/**
  * @}
  */

/** @addtogroup STM32F10x_System_Private_Functions
  * @{
  */

/**
  * @brief  Setup the microcontroller system
  *         Initialize the Embedded Flash Interface, the PLL and update the 
  *         SystemCoreClock variable.
  * @note   This function should be used only after reset.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
  RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
  RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
  /* Reset PLL2ON and PLL3ON bits */
  RCC->CR &= (uint32_t)0xEBFFFFFF;

  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x00FF0000;

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000;

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
    
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
  #ifdef DATA_IN_ExtSRAM
    SystemInit_ExtMemCtl(); 
  #endif /* DATA_IN_ExtSRAM */
#endif 

  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
  /* Configure the Flash Latency cycles and enable prefetch buffer */
  SetSysClock();
	
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif 


}

/**
  * @brief  Update SystemCoreClock according to Clock Register Values
  * @note   None
  * @param  None
  * @retval None
  */
void SystemCoreClockUpdate (void)
{
  uint32_t tmp = 0, pllmull = 0, pllsource = 0;

#ifdef  STM32F10X_CL
  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif /* STM32F10X_CL */

#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
  uint32_t prediv1factor = 0;
#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
    
  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;
  
  switch (tmp)
  {
    case 0x00:  /* HSI used as system clock */
      SystemCoreClock = HSI_VALUE;
      break;
    case 0x04:  /* HSE used as system clock */
      SystemCoreClock = HSE_VALUE;
      break;
    case 0x08:  /* PLL used as system clock */

      /* Get PLL clock source and multiplication factor ----------------------*/
      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
      
#ifndef STM32F10X_CL      
      pllmull = ( pllmull >> 18) + 2;
      
      if (pllsource == 0x00)
      {
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
      }
      else
      {
 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
       /* HSE oscillator clock selected as PREDIV1 clock entry */
       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
 #else
        /* HSE selected as PLL clock entry */
        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
        {/* HSE oscillator clock divided by 2 */
          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
        }
        else
        {
          SystemCoreClock = HSE_VALUE * pllmull;
        }
 #endif
      }
#else
      pllmull = pllmull >> 18;
      
      if (pllmull != 0x0D)
      {
         pllmull += 2;
      }
      else
      { /* PLL multiplication factor = PLL input clock * 6.5 */
        pllmull = 13 / 2; 
      }
            
      if (pllsource == 0x00)
      {
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
      }
      else
      {/* PREDIV1 selected as PLL clock entry */
        
        /* Get PREDIV1 clock source and division factor */
        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
        
        if (prediv1source == 0)
        { 
          /* HSE oscillator clock selected as PREDIV1 clock entry */
          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
        }
        else
        {/* PLL2 clock selected as PREDIV1 clock entry */
          
          /* Get PREDIV2 division factor and PLL2 multiplication factor */
          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
        }
      }
#endif /* STM32F10X_CL */ 
      break;

    default:
      SystemCoreClock = HSI_VALUE;
      break;
  }
  
  /* Compute HCLK clock frequency ----------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  /* HCLK clock frequency */
  SystemCoreClock >>= tmp;  
}

/**
  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
  * @param  None
  * @retval None
  */
static void SetSysClock(void)
{
#if defined SYSCLK_PREQ_USER
	SetSysClockTo48();
#endif
	
 
 /* If none of the define above is enabled, the HSI is used as System clock
    source (default after reset) */ 
}

/**
  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
  *          before jump to __main
  * @param  None
  * @retval None
  */ 
#ifdef DATA_IN_ExtSRAM
/**
  * @brief  Setup the external memory controller. 
  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
  *         board (STM32 High density devices). This SRAM will be used as program
  *         data memory (including heap and stack).
  * @param  None
  * @retval None
  */ 
void SystemInit_ExtMemCtl(void) 
{
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
  required, then adjust the Register Addresses */

  /* Enable FSMC clock */
  RCC->AHBENR = 0x00000114;
  
  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
  RCC->APB2ENR = 0x000001E0;
  
/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
/*----------------  SRAM Address lines configuration -------------------------*/
/*----------------  NOE and NWE configuration --------------------------------*/  
/*----------------  NE3 configuration ----------------------------------------*/
/*----------------  NBL0, NBL1 configuration ---------------------------------*/
  
  GPIOD->CRL = 0x44BB44BB;  
  GPIOD->CRH = 0xBBBBBBBB;

  GPIOE->CRL = 0xB44444BB;  
  GPIOE->CRH = 0xBBBBBBBB;

  GPIOF->CRL = 0x44BBBBBB;  
  GPIOF->CRH = 0xBBBB4444;

  GPIOG->CRL = 0x44BBBBBB;  
  GPIOG->CRH = 0x44444B44;
   
/*----------------  FSMC Configuration ---------------------------------------*/  
/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
  
  FSMC_Bank1->BTCR[4] = 0x00001011;
  FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */

#if defined SYSCLK_PREQ_USER



static void SetSysClockTo48(void)
{
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  /* Enable HSE */
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    StartUpCounter++;
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  }

  if (HSEStatus == (uint32_t)0x01)
  {
    /* Enable Prefetch Buffer */
    FLASH->ACR |= FLASH_ACR_PRFTBE;

    /* Flash 1 wait state */
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;

    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

    /* PCLK2 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

    /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

#ifdef STM32F10X_CL
    /* Configure PLLs ------------------------------------------------------*/
    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */

    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }


    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
                            RCC_CFGR_PLLMULL6);
#else
    /*  PLL configuration: PLLCLK = HSE * 4 = 48 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL4);
#endif /* STM32F10X_CL */
    /* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }

    /* Select PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock
         configuration. User can add here some code to deal with this error */
  }
}



static void SetSysClockToMy(void)
{
	 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  
  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
  /* Enable HSE */    
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    StartUpCounter++;  
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  }  

  if (HSEStatus == (uint32_t)0x01)
  {
    /* Enable Prefetch Buffer */
    FLASH->ACR |= FLASH_ACR_PRFTBE;

    /* Flash 2 wait state */
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    

 
    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; //ÅäÖÃAHB Prescaler
      
    /* PCLK2 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;//ÅäÖÃAPB2 Prescaler

#ifdef STM32F10X_CL
    /* Configure PLLs ------------------------------------------------------*/
    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ 
#if(SYSCLK_PREQ_CLOCK==20000000)
		/* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/8=5M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 4 = 20 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL4          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV8;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==24000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/10=4M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 6 = 24 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL6          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV10;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==25000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/8=5M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 5 = 25 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL5          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV8;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==28000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/10=4M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 7 = 28 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL7          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV10;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==30000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/8=5M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 6 = 30 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL6          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV8;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==32000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/10=4M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 8 = 32 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL8          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV10;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó 
#elif(SYSCLK_PREQ_CLOCK==40000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/5=8M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 5 = 40 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL5          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV5;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==45000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/8=5M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 9 = 45 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL9          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV8;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==48000000)
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_HSE | //Prediv1 Source MuxÑ¡ÔñΪHSE  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV1_DIV1 |   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV4 |   //Prediv2 ³ýµÄ±¶Êý Õⲿ·ÖÎÒÃÇûÓÐʹÓÃ,²»ÓÃÀí
                             RCC_CFGR2_PLL2MUL16 );     //PLL2Mul ³ËµÄ±¶Êý Õⲿ·ÖÎÒÃÇûÓÐʹÓÃ,²»ÓÃÀí
    //PLL =PREDIV1_CLK = 12M/1=12M
#if 0//ÎÒÃDz»ÐèÒªPLL2
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
#endif
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 4 = 48 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL4           //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
#elif(SYSCLK_PREQ_CLOCK==50000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/4=10M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 5 = 45 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL5          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV4;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==57600000)
		RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
		RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
													RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV4 | //Prediv2 ³ýµÄ±¶Êý
                             RCC_CFGR2_PLL2MUL16 |    //PLL2Mul ³ËµÄ±¶Êý
                             RCC_CFGR2_PREDIV1SRC_PLL2 | //Ñ¡ÔñPLL2×÷ΪPrediv1µÄÊäÈëÔ´
														 RCC_CFGR2_PREDIV1_DIV6);    //Prediv1 ³ýµÄ±¶Êý
    //PLL =PREDIV1_CLK = 12/4*16/6=8M
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
    
    //ÉÏÃæµÄÊÇÅäÖÃPLL2µÄ£¬ÎÒÃDz»Ó㬿ÉÒÔ²»Àí»á
		//ÏÂÃæµÄÊÇÅäÖÃPLL£¬ÎÒÃÇÐèÒª
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 6 = 48 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | //Prediv1 ³ýµÄ±¶Êý
		                        RCC_CFGR_PLLSRC_PREDIV1 |   //PLLÔ´£¬Ñ¡ÔñPrediv1(ÓÉ)
                            RCC_CFGR_PLLMULL6);         //±¶Æµ±¶Êý
#elif(SYSCLK_PREQ_CLOCK==60000000)
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_HSE | //Prediv1 Source MuxÑ¡ÔñΪHSE  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV1_DIV1 |   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV4 |   //Prediv2 ³ýµÄ±¶Êý Õⲿ·ÖÎÒÃÇûÓÐʹÓÃ,²»ÓÃÀí
                             RCC_CFGR2_PLL2MUL16 );     //PLL2Mul ³ËµÄ±¶Êý Õⲿ·ÖÎÒÃÇûÓÐʹÓÃ,²»ÓÃÀí
    //PLL =PREDIV1_CLK = 12M/1=12M
#if 0//ÎÒÃDz»ÐèÒªPLL2
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
#endif
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 5 = 60 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL5           //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
#elif(SYSCLK_PREQ_CLOCK==64000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/5=8 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 8 = 64 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL8          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV5;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==70000000)
	  /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//ÅäÖÃAPB1 Prescaler ´Ë×ÜÏßʱÖÓÓÐÉÏÏÞ
	  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_PLL2 | //Prediv1 Source MuxÑ¡ÔñΪPLL2  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV3 |   //Prediv2 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
                             RCC_CFGR2_PLL2MUL10 );     //PLL2Mul ³ËµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒ
    //PLL =PREDIV1_CLK = 12M/3*10/4=10M 
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
		
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 7 = 70 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL7          //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
		RCC->CFGR2 |= (uint32_t)RCC_CFGR2_PREDIV1_DIV4;   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª  //Õâ¸öÔÚʹÓÃPLL2ʱ£¬Ò»¶¨Òª·ÅÔÚ×îºó
#elif(SYSCLK_PREQ_CLOCK==72000000)        
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV1SRC_HSE | //Prediv1 Source MuxÑ¡ÔñΪHSE  Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV1_DIV1 |   //Prediv1 ³ýµÄ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														 RCC_CFGR2_PREDIV2_DIV4 |   //Prediv2 ³ýµÄ±¶Êý Õⲿ·ÖÎÒÃÇûÓÐʹÓÃ,²»ÓÃÀí
                             RCC_CFGR2_PLL2MUL16 );     //PLL2Mul ³ËµÄ±¶Êý Õⲿ·ÖÎÒÃÇûÓÐʹÓÃ,²»ÓÃÀí
    //PLL =PREDIV1_CLK = 12M/1=12M
#if 0//ÎÒÃDz»ÐèÒªPLL2
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
#endif
    /* PLL configuration: PLLCLK = PREDIV1_CLK * 6 = 72 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1   | //PLL Source Mux Ñ¡ÔñPrediv1×÷ΪÊäÈëÔ´ Õâ¸öÎÒÃÇÐèÒª
                            RCC_CFGR_PLLMULL6           //±¶Æµ±¶Êý Õâ¸öÎÒÃÇÐèÒª
														//RCC_CFGR_PLLXTPRE_PREDIV1 //Õâ¸ö²»Ã÷°×ÊÇÅäÖÃÄĸöµÄ
														);
#else
		#error "ÇëÑ¡ÔñƵÂÊ"
#endif
#else    
    /*  PLL configuration: PLLCLK = HSE * 6 = 72 MHz */
		
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |RCC_CFGR_PLLMULL));
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
#endif /* STM32F10X_CL */

    /* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }
    
    /* Select PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;//System Clock MuxÑ¡Ôñ
		
    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock 
        configuration. User can add here some code to deal with this error */
		g_ucHSE_Flag=0;
		while(1);
  }
}
#endif

/**
  * @}
  */

/**
  * @}
  */
  
/**
  * @}
  */    
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/